Kioxia pushes 100 million IOPS flash drive target to 2028 due to PCIe 7.0 certification timeline

Kioxia has confirmed that its next-generation XL-Flash Gen 3 storage class memory, paired with the PCIe 7.0 interface, will now target 100 million random read IOPS by 2028, reflecting a one-year slip from its original 2027 goal. This adjustment is driven by the time required for the PCIe 7.0 ecosystem to complete official compliance certification, rather than any issues with the flash silicon itself. While Kioxia's technology is ready, the 100 million IOPS performance physically requires the massive bandwidth of PCIe 7.0, which is scheduled for official Integrators List certification by PCI-SIG only in 2028.

Previously, Kioxia demonstrated evaluation samples of its GP1 Series SSD at FMS 2026 on August 4, delivering 10 million IOPS using second-generation XL-Flash over a PCIe 6.0 interface. The tenfold jump to 100 million IOPS in the next generation requires simultaneously solving constraints across the flash's internal parallelism, controller architecture, and host interface bandwidth. Utilizing single-level cell (SLC) mode, XL-Flash achieves sub-5-microsecond read latency, 512-byte access granularity, and high endurance of 150,000 to 250,000 program-erase cycles per cell, significantly outperforming standard enterprise TLC or QLC SSDs.

This technology is designed to solve the key-value (KV) cache bottleneck generated during large language model (LLM) inference. When processing long contexts, the KV cache of a 70-billion-parameter model can exceed 320 gigabytes, which is four times the total high-bandwidth memory (HBM) capacity of an Nvidia H100 GPU. Kioxia's GP1 SSD, integrated into Nvidia's Storage-Next initiative, addresses this by providing a high-speed, cost-effective overflow tier that offloads warm KV cache data from GPU memory to flash storage without stalling the inference pipeline.

Kioxia is not the only player in this emerging tier, as competitors SK Hynix and SanDisk published the technical specification for High Bandwidth Flash (HBF) through the Open Compute Project (OCP) in August 2026. Unlike Kioxia's PCIe-attached SSD design, HBF vertically stacks NAND dies using through-silicon vias (TSV) and connects directly to accelerators via the UCIe interconnect. To hedge against this unsettled architectural race, Kioxia is simultaneously pursuing multiple paths, having shipped evaluation samples of its XL-Flash-based CXL memory expansion module (XL1) and developing its own TSV-stacked high-bandwidth flash solutions.